Estimation of chip floorplan activity distribution
US10430545B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Nov 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.