ARTERIS, INC.
🏢 View company profile →91Patents
90Active
91Granted
56Portfolio score
Filing activity: Aug 11, 2004 → Jul 15, 2024 · 7 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7574629B2 | Method and device for switching between agents | Physics | 19 | Active |
| US11121933B2 | Physically aware topology synthesis of a network | Physics | 19 | Active |
| US10990724B1 | System and method for incremental topology synthesis of a network-on-chip | Physics | 18 | Active |
| US9825779B2 | Network-on-chip (NoC) topology generation | Physics | 17 | Active |
| US11281827B1 | Optimization of parameters for synthesis of a topology using a discriminant function module | Physics | 16 | Active |
| US9940423B2 | Editing a NoC topology on top of a floorplan | Physics | 16 | Active |
| US11449655B2 | Synthesis of a network-on-chip (NoC) using performance constraints and objectives | Physics | 13 | Active |
| US10528421B2 | Protection scheme conversion | Physics | 6 | Active |
| US7769027B2 | Method and device for managing priority during the transmission of a message | Electricity | 5 | Active |
| US10949585B1 | System and method for predicting performance, power and area behavior of soft IP components in integrated circuit design | Physics | 5 | Active |
| US9542316B1 | System and method for adaptation of coherence models between agents | Physics | 5 | Active |
| US10146615B2 | Recovery of a system directory after detection of uncorrectable error | Physics | 3 | Active |
| US9652391B2 | Compression of hardware cache coherent addresses | Physics | 3 | Active |
| US7148728B2 | Digital delay device, digital oscillator clock signal generator and memory interface | Electricity | 3 | Expired |
| US10902166B2 | System and method for isolating faults in a resilient system | Electricity | 3 | Active |
| US11210445B1 | System and method for interface protection | Physics | 3 | Active |
| US8441931B2 | Method and device for managing priority during the transmission of a message | Electricity | 2 | Active |
| US10877839B2 | Recovery of a coherent system in the presence of an uncorrectable error | Emerging Cross-Sectional Technologies | 2 | Active |
| US8254380B2 | Managing messages transmitted in an interconnect network | Electricity | 2 | Active |
| US10592358B2 | Functional interconnect redundancy in cache coherent systems | Physics | 1 | Active |
| US10803223B2 | System and method for designing a chip floorplan using machine learning | Physics | 1 | Active |
| US10025677B2 | Redundancy for cache coherence systems | Physics | 1 | Active |
| US11601357B2 | System and method for generation of quality metrics for optimization tasks in topology synthesis of a network | Physics | 1 | Active |
| US11657203B2 | Multi-phase topology synthesis of a network-on-chip (NoC) | Physics | 1 | Active |
| US12093177B2 | Multi-level partitioned snoop filter | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.