Processor with memory array operable as either last level cache slice or neural network unit memory
US10430706B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2016 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Apr 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1041
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising a plurality of processing cores, a last level cache memory (LLC) shared by the plurality of processing cores, and a neural network unit (NNU) comprising an array of neural processing units (NPU) and a memory array. The LLC comprises a plurality of slices. To transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor write-back-invalidates the LLC and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices. To transition from the second mode to the first mode, the processor write-back-invalidates the LLC and updates the hashing algorithm to exclude the memory array from the LLC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.