Douglas R. Reed
36Patents
6h-index
12Co-inventors
58Inventor score
Filing activity: Feb 4, 2013 → Jan 21, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9811468B2 | Set associative cache memory with heterogeneous replacement policy | Emerging Cross-Sectional Technologies | 37 | Active |
| US9892803B2 | Cache management request fusing | Physics | 25 | Active |
| US10430706B2 | Processor with memory array operable as either last level cache slice or neural network unit memory | Physics | 23 | Active |
| US10664751B2 | Processor with memory array operable as either cache memory or neural network unit memory | Physics | 13 | Active |
| US10423876B2 | Processor with memory array operable as either victim cache or neural network unit memory | Physics | 8 | Active |
| US9972375B2 | Sanitize-aware DRAM controller | Emerging Cross-Sectional Technologies | 7 | Active |
| US9652398B2 | Cache replacement policy that considers memory access type | Physics | 5 | Active |
| US11467972B2 | L1D to L2 eviction | Physics | 2 | Active |
| US9817764B2 | Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type | Physics | 2 | Active |
| US10127041B2 | Compiler system for a processor with an expandable instruction set architecture for dynamically configuring execution resources | Physics | 2 | Active |
| US10387318B2 | Prefetching with level of aggressiveness based on effectiveness by memory access type | Emerging Cross-Sectional Technologies | 2 | Active |
| US9910785B2 | Cache memory budgeted by ways based on memory access type | Emerging Cross-Sectional Technologies | 2 | Active |
| US10725934B2 | Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode | Physics | 2 | Active |
| US11029949B2 | Neural network unit | Physics | 1 | Active |
| US9911508B2 | Cache memory diagnostic writeback | Physics | 1 | Active |
| US9798668B2 | Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode | Emerging Cross-Sectional Technologies | 1 | Active |
| US9575816B2 | Deadlock/livelock resolution using service processor | Physics | 1 | Active |
| US10719434B2 | Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode | Emerging Cross-Sectional Technologies | 1 | Active |
| US9652400B2 | Fully associative cache memory budgeted by memory access type | Physics | 1 | Active |
| US9898411B2 | Cache memory budgeted by chunks based on memory access type | Physics | 1 | Active |
| US10268586B2 | Processor with programmable prefetcher operable to generate at least one prefetch address based on load requests | Physics | 0 | Active |
| US10642617B2 | Processor with an expandable instruction set architecture for dynamically configuring execution resources | Physics | 0 | Active |
| US12380033B2 | Refreshing cache regions using a memory controller and multiple tables | Physics | 0 | Active |
| US11940921B2 | Bounding box prefetcher | Emerging Cross-Sectional Technologies | 0 | Active |
| US10073787B2 | Dynamic powering of cache memory by ways within multiple set groups based on utilization trends | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.