Method and apparatus for controlling access to a common bus by multiple components
US10431292B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.