Memory cell size reduction for scalable logic gate non-volatile memory arrays
US10431308B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Aug 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Scalable Logic Gate Non-Volatile Memory (LGNVM) NOR-type arrays fabricated by the standard CMOS logic technologies have been applied for the embedded flash solutions in digital circuitries. To significantly reduce the memory array sizes from the previous fabrications, we have applied the topological regularity of memory cells in the arrays and a self-aligned etch process step to eliminate the gate end-caps in the memory areas. Without scarifying the memory array yields, the minimal unit cell size of 12 F2 for the LGNVM NOR flash arrays can be achieved by this method, where F is the minimal feature size for a specific CMOS logic process technology node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.