Lee Wang
50Patents
6h-index
10Co-inventors
69Inventor score
Filing activity: Jun 16, 1997 → Feb 14, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5824584A | Method of making and accessing split gate memory device | Emerging Cross-Sectional Technologies | 65 | Expired |
| US7099192B2 | Nonvolatile flash memory and method of operating the same | Physics | 45 | Expired |
| US7729165B2 | Self-adaptive and self-calibrated multiple-level non-volatile memories | Physics | 15 | Active |
| US8817546B2 | Complementary electrical erasable programmable read only memory | Physics | 15 | Active |
| US7733700B2 | Method and structures for highly efficient hot carrier injection programming for non-volatile memories | Physics | 10 | Active |
| US8716803B2 | 3-D single floating gate non-volatile memory device | Electricity | 8 | Active |
| US9754668B1 | Digital perceptron | Physics | 6 | Active |
| US7400527B2 | Bit symbol recognition method and structure for multiple bit storage in non-volatile memories | Physics | 5 | Active |
| US9048137B2 | Scalable gate logic non-volatile memory cells and arrays | Electricity | 5 | Active |
| US7859903B1 | Methods and structures for reading out non-volatile memory using NVM cells as a load element | Physics | 5 | Active |
| US8415721B2 | Field side sub-bitline nor flash array and method of fabricating the same | Electricity | 5 | Active |
| US9779814B2 | Non-volatile static random access memory devices and methods of operations | Physics | 4 | Active |
| US10431308B1 | Memory cell size reduction for scalable logic gate non-volatile memory arrays | Electricity | 3 | Active |
| US9082490B2 | Ultra-low power programming method for N-channel semiconductor non-volatile memory | Physics | 3 | Active |
| US7515465B1 | Structures and methods to store information representable by a multiple bit binary word in electrically erasable, programmable read-only memories (EEPROM) | Physics | 3 | Active |
| US7626868B1 | Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM) | Physics | 3 | Active |
| US7995398B2 | Structures and methods for reading out non-volatile memories | Physics | 3 | Active |
| US9502113B2 | Configurable non-volatile content addressable memory | Physics | 3 | Active |
| US8274828B2 | Structures and methods for reading out non-volatile memory using referencing cells | Physics | 2 | Active |
| US8988104B2 | Multiple-time configurable non-volatile look-up-table | Electricity | 2 | Active |
| US9685239B1 | Field sub-bitline nor flash array | Electricity | 2 | Active |
| US8415735B2 | Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same | Electricity | 2 | Active |
| US7660154B2 | Level verification and adjustment for multi-level cell (MLC) non-volatile memory (NVM) | Physics | 2 | Active |
| US7606069B2 | Bit-symbol recognition method and structure for multiple-bit storage in non-volatile memories | Physics | 2 | Active |
| US9214465B2 | Structures and operational methods of non-volatile dynamic random access memory devices | Electricity | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.