Embedded transconductance test circuit and method for flash memory cells
US10431321B1 · kind B1 · utility
1Cited by
1References
18Claims
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Key dates
| Filing date | Jun 26, 2018 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5606
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transconductance test method implemented in a flash memory device detects memory cells with low transconductance and provides an output identifying memory cells, if any, having been classified as having a low transconductance (low gm). In some embodiments, the transconductance test method implements multi-step testing using a pair of gate bias levels for each test step. Accurate detection of memory cells with low transconductance can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.