Integrated Silicon Solution, (Cayman) Inc.
55Patents
55Active
55Granted
53Portfolio score
Filing activity: Dec 28, 2017 → Feb 8, 2023
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11417829B2 | Three dimensional perpendicular magnetic tunnel junction with thin film transistor array | Electricity | 1 | Active |
| US10911044B1 | Wide range output driver circuit for semiconductor device | Electricity | 1 | Active |
| US11621027B2 | MRAM architecture with multiplexed sense amplifiers and direct write through buffers | Physics | 1 | Active |
| US10431321B1 | Embedded transconductance test circuit and method for flash memory cells | Physics | 1 | Active |
| US11329217B2 | Method for manufacturing a magnetic random-access memory device using post pillar formation annealing | Electricity | 0 | Active |
| US11545524B2 | Selector transistor with continuously variable current drive | Electricity | 0 | Active |
| US12029045B2 | Multi terminal device stack systems and methods | Electricity | 0 | Active |
| US11626407B2 | DRAM with selective epitaxial cell transistor | Electricity | 0 | Active |
| US11626559B2 | Multi terminal device stack formation methods | Electricity | 0 | Active |
| US12069957B2 | Method for manufacturing a magnetic random-access memory device using post pillar formation annealing | Electricity | 0 | Active |
| US11580014B2 | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments | Emerging Cross-Sectional Technologies | 0 | Active |
| US11386010B2 | Circuit engine for managing memory meta-stability | Emerging Cross-Sectional Technologies | 0 | Active |
| US11442875B2 | Arbitration control for pseudostatic random access memory device | Electricity | 0 | Active |
| US11714762B2 | Arbitration control for pseudostatic random access memory device | Electricity | 0 | Active |
| US11574194B2 | System and method for training neural networks with errors | Physics | 0 | Active |
| US12069964B2 | Three dimensional perpendicular magnetic tunnel junction with thin film transistor array | Electricity | 0 | Active |
| US11586906B2 | System and method for training artificial neural networks | Physics | 0 | Active |
| US11444123B2 | Selector transistor with metal replacement gate wordline | Electricity | 0 | Active |
| US11329099B2 | Magnetic memory chip having nvm class and SRAM class MRAM elements on the same chip | Electricity | 0 | Active |
| US12182697B2 | System and method for training artificial neural networks | Physics | 0 | Active |
| US11302697B2 | DRAM with selective epitaxial cell transistor | Electricity | 0 | Active |
| US11723217B2 | Magnetic tunnel junction element with RU hard mask for use in magnetic random-access memory | Electricity | 0 | Active |
| US11688649B2 | Compact and efficient CMOS inverter | Electricity | 0 | Active |
| US10984872B1 | Non-volatile memory with source line resistance compensation | Physics | 0 | Active |
| US11302586B2 | Compact and efficient CMOS inverter | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.