Semiconductor device, layout pattern and method for manufacturing an integrated circuit
US10431541B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2017 |
| Grant date | Oct 1, 2019 |
| Priority date | — |
| Expiry date | May 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device for fabricating an IC is provided. The semiconductor device includes an interconnect structure and a first conductive line. The interconnect structure is made of conductive material and includes a first interconnect portion and a second interconnect portion. The second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion. The first conductive line is arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure. A distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.