Inventor · Baoshan, TW

Hsin Chang

19Patents
4h-index
22Co-inventors
60Inventor score

Filing activity: Aug 19, 1999 → Aug 9, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8643148B2 Chip-on-Wafer structures and methods for forming the same Electricity 305 Active
US6059161A Assembly of a power stapler Performing Operations; Transporting 27 Expired
US8928159B2 Alignment marks in substrate having through-substrate via (TSV) Electricity 21 Active
US9123643B2 Chip-on-wafer structures and methods for forming the same Electricity 4 Active
US8567837B2 Reconfigurable guide pin design for centering wafers having different sizes Emerging Cross-Sectional Technologies 2 Active
US8962481B2 Chip-on-wafer structures and methods for forming the same Electricity 2 Active
US11616002B2 Through-circuit vias in interconnect structures Electricity 2 Active
US10163706B2 Alignment marks in substrate having through-substrate via (TSV) Electricity 1 Active
US10692764B2 Alignment marks in substrate having through-substrate via (TSV) Electricity 1 Active
US10777510B2 Semiconductor device including dummy via anchored to dummy metal layer Electricity 1 Active
US9449919B2 Semiconductor device, layout design and method for manufacturing a semiconductor device Physics 0 Active
US12293959B2 Through-circuit Vias in interconnect structures Electricity 0 Active
US11955441B2 Interconnect structure and forming method thereof Electricity 0 Active
US9941159B2 Method of manufacturing a semiconductor device Physics 0 Active
US11302654B2 Method of fabricating semiconductor device including dummy via anchored to dummy metal layer Electricity 0 Active
US9099515B2 Reconfigurable guide pin design for centering wafers having different sizes Emerging Cross-Sectional Technologies 0 Active
US10910267B2 Alignment marks in substrate having through-substrate via (TSV) Electricity 0 Active
US10431541B2 Semiconductor device, layout pattern and method for manufacturing an integrated circuit Electricity 0 Active
US12243805B2 Through-circuit vias in interconnect structures Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.