Apparatuses and methods for exiting low power states in memory devices
US10437307B2 · kind B2 · utility
1Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Nov 3, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, an apparatus is disclosed. The apparatus includes a memory device having a device identification. The apparatus further includes a low power wake circuit configured to receive a low power wake signal and an identification information, and further configured to initiate a transition of the memory device from a low power state to an active state responsive to an active low power wake signal and the wake identification information matching the device identifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.