Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system
US10437592B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Nov 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Reduced logic level operation folding of context history in a history register in a prediction system for a processor-based system is disclosed. The prediction system includes a prediction circuit employing reduced operation folding of the history register for indexing a prediction table containing prediction values used to process a consumer instruction when value has not yet been resolved. To avoid the requirement to perform successive logic folding operations to produce a folded context history of a resultant reduced bit width, reduced logic level folding operation of the resultant reduced bit width is employed. Reduced logic level folding operation of the resultant reduced bit width involves using current folded context history from previous contents of a history register as basis for determining a new folded context history. In this manner, logic folding of the history register is faster and operates with reduced power consumption as a result of fewer logic operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.