System and method for performing a concurrent multiple page read of a memory array
US10438656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Dec 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for facilitating multiple concurrent page reads in a memory array is provided. Memory cells that have multiple programming states (e.g., store multiple bits per cell) rely on various control gate and wordline voltages levels to read the memory cells. Therefore, to concurrently read multiple pages of memory cells, where each page includes one or more different programming levels, a memory controller includes first wordline control logic that includes a first voltage regulator and includes second wordline control logic that includes a second voltage regulator, according to one embodiment. The two voltage regulators enable the memory controller to concurrently address and access multiple pages of memory at different programming levels, in response to memory read requests, according to one embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.