Metal interconnect structure and method for fabricating the same
US10438893B2 · kind B2 · utility
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2References
16Claims
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Key dates
| Filing date | Oct 15, 2017 |
| Grant date | Oct 8, 2019 |
| Priority date | — |
| Expiry date | Oct 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first inter-metal dielectric (IMD) layer thereon; forming a first metal interconnection and a second metal interconnection in the first IMD layer; removing part of the first IMD layer to form a recess between the first metal interconnection and the second metal interconnection; performing a curing process; and forming a second IMD layer on the first metal interconnection and the second metal interconnection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.