Methods and apparatus to facilitate field-programmable gate array support during runtime execution of computer readable instructions
US10445118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, systems, and articles of manufacture to facilitate field-programmable gate array support during runtime execution of computer readable instructions are disclosed herein. An example apparatus includes a compiler to, prior to runtime, compile a block of code written as high level source code into a first hardware bitstream kernel and a second hardware bitstream kernel; a kernel selector to select the first hardware bitstream kernel based on an attribute to be dispatched during runtime; a dispatcher to dispatch the first hardware bitstream kernel to a field programmable gate array (FPGA) during runtime; and the kernel selector to, when an FPGA attribute does not satisfy a threshold during runtime, adjust the selection of the first hardware bitstream kernel to the second hardware bitstream kernel to be dispatched during runtime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.