Yipeng Wang
27Patents
5h-index
76Co-inventors
68Inventor score
Filing activity: Nov 19, 2012 → Dec 22, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10598852B1 | Digital-to-analog converter (DAC)-based driver for optical modulators | Physics | 17 | Active |
| US10712770B1 | Clock phase aligner for high speed data serializers | Physics | 8 | Active |
| US10445118B2 | Methods and apparatus to facilitate field-programmable gate array support during runtime execution of computer readable instructions | Physics | 8 | Active |
| US9846627B2 | Systems and methods for modeling memory access behavior and memory traffic timing behavior | Physics | 5 | Active |
| US10530375B1 | High speed frequency divider | Electricity | 5 | Active |
| US10445271B2 | Multi-core communication acceleration using hardware queue device | Physics | 4 | Active |
| US10216668B2 | Technologies for a distributed hardware queue manager | Physics | 3 | Active |
| US8709753B2 | Native NAD-dependent GAPDH replaced with NADP-dependent GAPDH plus NADK | Chemistry; Metallurgy | 3 | Active |
| US10789176B2 | Technologies for a least recently used cache replacement policy using vector instructions | Emerging Cross-Sectional Technologies | 2 | Active |
| US11146262B1 | Low-noise reference voltage generator | Electricity | 2 | Active |
| US11824534B2 | Transmit driver architecture with a jtag configuration mode, extended equalization range, and multiple power supply domains | Electricity | 1 | Active |
| US11088951B2 | Flow classification apparatus, methods, and systems | Electricity | 1 | Active |
| US10845995B2 | Techniques to control an insertion ratio for a cache | Physics | 1 | Active |
| US11201940B2 | Technologies for flow rule aware exact match cache compression | Physics | 0 | Active |
| US11698929B2 | Offload of data lookup operations | Physics | 0 | Active |
| US12186400B2 | Micromolecular compound specifically degrading tau protein, and application thereof | Chemistry; Metallurgy | 0 | Active |
| US11392298B2 | Techniques to control an insertion ratio for a cache | Physics | 0 | Active |
| US12210434B2 | Apparatus and method for a closed-loop dynamic resource allocation control framework | Physics | 0 | Active |
| US11811660B2 | Flow classification apparatus, methods, and systems | Electricity | 0 | Active |
| US10929323B2 | Multi-core communication acceleration using hardware queue device | Physics | 0 | Active |
| US11709774B2 | Data consistency and durability over distributed persistent memory systems | Physics | 0 | Active |
| US12197601B2 | Hardware offload circuitry | Physics | 0 | Active |
| US10719442B2 | Apparatus and method for prioritized quality of service processing for transactional memory | Physics | 0 | Active |
| US11601531B2 | Sketch table for traffic profiling and measurement | Electricity | 0 | Active |
| US11500825B2 | Techniques for dynamic database access modes | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.