Simulation-assisted wafer rework determination
US10445452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/20
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Aspects of the disclosed technology relate to techniques for using hotspot simulation to make wafer rework decisions. Metrology data of photoresist patterns created based on a layout design for a circuit design by a photolithographic processing step are received during a lithographic process. Hotspots of interest are selected based on comparing the metrology data with simulated metrology data associated with hotspots. The simulated metrology data and information of the hotspots are generated by performing lithographic simulation on the layout design before the lithographic process and stored in a library of potential hotspots. Lithography simulation is performed on the selected hotspots of interest using process conditions of the photolithographic processing step to generate simulated hotspot data. The simulated hotspot data are analyzed to determine whether rework of the one or more wafers or a wafer lot to which the one or more wafers belong is needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.