Read circuit for a variable resistance memory device
US10446227B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a memory device includes: a memory cell including a variable resistance element and connected between a word line and a bit line; and a control circuit configured to control an operation of the memory cell. The variable resistance element includes: a first layer including a first compound including oxygen; a second layer including a second compound including oxygen; and a third layer between the first layer and the second layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.