In-line protection from process induced dielectric damage
US10446436B2 · kind B2 · utility
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15References
25Claims
0Family size
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Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Nov 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1031
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a dielectric layer and a second conductive shape on a second portion of the dielectric layer. A conductive trace is formed over at least a portion of the second conductive shape. The conductive trace electrically connects the first conductive shape with a substrate tie. An interconnect layer is coupled to the first conductive shape. The conductive trace is etched to electrically isolate the first conductive shape from the substrate tie.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.