Patent · US Active

Packaged integrated circuit having stacked die and method for therefor

US10446476B2 · kind B2 · utility

3Cited by

9References

17Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Leo M. Higgins, III · Austin, US
Fred T. Brauchler · Canton, US
Burton J. Carpenter · Austin, US
Jinmei Liu · Tianjin, CN
Mariano Layson Ching, Jr. · Tianjin, CN
Jinzhong Yao · Tianjin, CN
Xingshou Pang · Tianjin, CN
Jianhong Wang · Shanxi, CN
Yadong Wei · Jingwei, CN

Key dates

Filing date	Mar 19, 2018
Grant date	Oct 15, 2019
Priority date	—
Expiry date	Mar 19, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH04L25/0266
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.