Wafer level package and manufacturing method thereof
US10446506B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H9/1064
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level package includes a substrate including bonding pads and a first protection dam and having a plurality of circuit pattern units disposed on a side; a printed circuit board having a plurality of connection pads, a second protection dam and via holes disposed thereon; and a connection unit connected to some of the plurality of connection pads and the second protection dam disposed on the printed circuit board. Freedom of design can be improved through the wafer level package and the manufacturing method thereof, and reliability of the wafer level package can be improved. The manufacturing process can be simplified as the bridge process is omitted when wiring is designed, and the size of an element may be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.