Optimal LDPC bit flip decision
US10447301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2017 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid state storage device comprises a non-volatile memory controller configured to store data in a non-volatile memory, wherein the stored data is encoded using a first error-correcting code and a second Low Density Parity Check (LDPC) code. The non-volatile memory controller includes a hard-decision LDPC decoder to decode encoded data received from the non-volatile memory and provide a decoded data output. The hard-decision LDPC decoder selects a voting scheme at each iteration in a sequence of iterations of decoding to determine when to implement bit flipping at a variable node amongst a plurality of check nodes, each of the plurality of check nodes connected to a plurality of variable nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.