Multi-bias level generation and interpolation
US10447508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2018 |
| Grant date | Oct 15, 2019 |
| Priority date | — |
| Expiry date | Jan 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03363
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A device includes a first bias level generator to generate a first bias level of a plurality of bias levels and transmit the bias level having a first voltage value, a second bias level generator to generate a second bias level of the plurality of bias levels and transmit the second bias level having a second voltage value. The device also includes a voltage divider that interpolates a subset of bias levels of the plurality of bias levels between the first bias level and the second bias level and supplies a selected bias level of the plurality of bias levels a control signal to an adjustment circuit of a decision feedback equalizer to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.