Combining states of multiple threads in a multi-threaded processor
US10452396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 1, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Feb 17, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising: an execution unit, multiple context register sets, a scheduler arranged to control the execution unit to provide a repeating sequence of temporally interleaved time slots, thereby enabling at least one respective worker thread to be allocated for execution in each respective one of some or all of the time slots, wherein a program state of the respective worker thread currently executing in each time slot is maintained in a respective one of the context register sets; and an exit state register arranged to store an aggregated exit state the worker threads. The instruction set comprises an exit instruction for inclusion in each worker thread, the exit state instruction taking an individual exit state of the respective thread as an operand. The exit instruction terminates the respective worker and also cause the individual exit state specified in the operand to contribute to the aggregated exit state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.