Inventor · Malmesbury, GB

Simon Knowles

58Patents
4h-index
26Co-inventors
66Inventor score

Filing activity: Oct 29, 1991 → Mar 17, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US6446107B1 Circuitry for performing operations on binary numbers Physics 52 Expired
US7933405B2 Data access and permute unit Physics 25 Active
US5243551A Processor suitable for recursive computations Physics 15 Expired
US5235537A Digital processor for two's complement computations Physics 13 Expired
US8484442B2 Apparatus and method for control processing in dual path processor Physics 4 Active
US7949856B2 Method and apparatus for separate control processing and data path processing in a dual path processor with a shared load/store unit Physics 4 Expired
US9047094B2 Apparatus and method for separate asymmetric control processing and data path processing in a dual path processor Physics 4 Active
US8782376B2 Vector instruction execution to load vector data in registers of plural vector units using offset addressing logic Physics 3 Active
US8484441B2 Apparatus and method for separate asymmetric control processing and data path processing in a configurable dual path processor that supports instructions having different bit widths Physics 3 Expired
US8966223B2 Apparatus and method for configurable processing Physics 3 Active
US10452396B2 Combining states of multiple threads in a multi-threaded processor Physics 2 Active
US10585716B2 Parallel computing Physics 2 Active
US6519622B1 Designing addition circuits Physics 2 Expired
US10606641B2 Scheduling tasks in a multi-threaded processor Physics 2 Active
US10564970B2 Synchronization in a multi-tile processing arrangement Physics 1 Active
US11321272B2 Instruction set Physics 1 Active
US11023290B2 Synchronization amongst processor tiles Physics 1 Active
US8671268B2 Apparatus and method for configurable processing Physics 1 Active
US11467833B2 Load-store instruction for performing multiple loads, a store, and strided increment of multiple addresses Physics 1 Active
US10936008B2 Synchronization in a multi-tile processing array Physics 1 Active
US7780250B2 Collapsible bar Human Necessities 1 Active
US10963003B2 Synchronization in a multi-tile processing array Physics 1 Active
US12273268B2 Computer system having a chip configured for memory attachment and routing Electricity 0 Active
US11900109B2 Instruction for masking randomly selected values in a source vector for neural network processing Physics 0 Active
US12346284B2 Network computer with external memory Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.