Patent · US Active

Fault insertion for system verification

US10452797B2 · kind B2 · utility

3Cited by

10References

16Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Michael G. Smith · Austin, US
David R. Smith · Durham, US
Mohammad Omair Abbasi · Beaverton, US
Vivian An · Portland, US

Key dates

Filing date	Oct 31, 2014
Grant date	Oct 22, 2019
Priority date	—
Expiry date	Oct 31, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/367
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A computer implemented method of modifying a compiled design of an electronic circuit is disclosed. The method includes accessing a stored compilation representing the design, and causing the computer to generate a modified version of the stored compilation in response to an indication of a change to a portion of the design.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.