Hybrid LPDDR4-DRAM with cached NVM and flash-NAND in multi-chip packages for mobile devices
US10453501B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Mar 6, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.