Patent · US Active

Low damage low-k dielectric etch

US10453700B2 · kind B2 · utility

1Cited by
1References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateDec 18, 2015
Grant dateOct 22, 2019
Priority date—
Expiry dateDec 18, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76826
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A method of forming an interconnect structure for an integrated circuit. A dielectric stack is formed on the substrate including an etch-stop layer, a low-k or ULK dielectric layer, and a hard mask layer. The low-k or ULK dielectric is etched using at least two etching processes wherein each etching process is followed by an etch repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma. The photoresist may be removed using at least two ashing processes wherein each ashing process is followed by an ash repair process where the etch repair process includes flowing at least one hydrocarbon into the reactor and generating a plasma.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.