Barrier layer removal method and semiconductor structure forming method
US10453743B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2014 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Oct 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76865
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.