Method of manufacturing a gate-all-around semiconductor device
US10453752B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/125
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A fin including a bottom portion, a first sacrificial layer disposed over the bottom portion, a first semiconductor layer disposed over the first sacrificial layer, a second sacrificial layer disposed over the first semiconductor layer and a second semiconductor layer disposed over the second sacrificial layer, is formed. The second semiconductor layer protrudes from a first insulating layer. A dummy gate is formed over the second semiconductor layer. A sidewall spacer layer is formed on side faces of the dummy gate. A first dielectric layer is formed over the dummy gate and the sidewall spacer layer. The dummy gate is removed, thereby forming a gate space. The first insulating layer is etched in the gate space, thereby exposing the first semiconductor layer and the first and second sacrificial layers. The first and second sacrificial layers are removed. A gate dielectric layer and a gate electrode layer are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.