Wiring substrate having alternating ground and signal lines in a plurality of wiring layers
US10453803B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wiring substrate includes a first wiring layer, a second wiring layer stacked on the first wiring layer, and a dielectric layer sandwiched between the first wiring layer and the second wiring layer. The first wiring layer includes first signal lines and first grounding lines which are interleaved and spaced apart in the first wiring layer. The second wiring layer includes second signal lines and second grounding lines which are interleaved and spaced apart in the second wiring layer. An orthographic projection of one of the second signal lines to the first wiring layer is located between each two adjacent ones of the first signal lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.