Lateral DMOS device with dummy gate
US10453955B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.