Execution of load instructions in a processor
US10459725B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2016 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for executing a load instruction in a processor are described. In one example, load instructions which are detected to have an offset (or displacement) of zero are sent directly to a data cache, bypassing the address generation stage thereby reducing pipeline length. Load instructions having a nonzero offset can be executed in an address generation stage as is conventional. To avoid conflicts between a current load instruction with zero offset and a previous load instruction with nonzero offset, the current instruction can be rescheduled or sent through a separate dedicated load pipe. An alternative technique permits a load instruction with zero offset to be issued one cycle earlier than it would need to be if it had a nonzero offset, thus reducing load latency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.