Error detection for training non-volatile memories
US10459785B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Nov 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure, in various embodiments, describes technologies and techniques for detecting errors in a non-volatile memory (NVM) device prior to performing re-training/recalibration. A processing device in a NVM controller detects a cyclic redundancy check (CRC) condition for detecting error in the NVM device, and a re-training condition that is based on the CRC condition. A CRC circuit generates CRC code when a CRC condition is detected, and the processing is configured to compare CRC code received from the NVM controller with the generated CRC code to detect error. A calibration circuit then re-trains the NVM device if the CRC circuit detects error and the re-training condition has been met.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.