Stacked memory chip device with enhanced data protection capability
US10459809B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Jun 30, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.