Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank
US10460781B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1697
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.