Memory cell and methods thereof

US10460788B2 · kind B2 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventor

• Stefan Müller · Wetzlar, DE

Key dates

• Filing date: Oct 27, 2017
• Grant date: Oct 29, 2019
• Expiry date: Oct 27, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

According to various embodiments, a memory cell may include: a channel region, a gate isolation structure disposed at the channel region; and a memory structure disposed over the gate isolation structure, the memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure, the gate isolation structure, and the channel region form a first capacitor structure defining a capacitor area of a first size; and wherein the first electrode structure, the at least one remanent-polarizable layer, and the second electrode structure form a second capacitor structure defining a capacitor area of a second size, wherein the second size is less than the first size.