Non-volatile memory and method for power efficient read or verify using lockout control
US10460814B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 12, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.