Semiconductor apparatus with reduced risks of chip counterfeiting and network invasion
US10460824B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Sep 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus includes a semiconductor chip, with the semiconductor chip including a modular region and a test circuit. The modular region includes a plurality of modular areas each including a memory cell array with redundant bit lines and a peripheral memory area storing at least redundant addresses. The test circuit retrieves the redundant addresses intrinsic to the semiconductor chip. The distribution of the redundant addresses is randomly formed related to a part or an entirety of the modular area of the modular region. The distribution of the retrieved redundant addresses is irreversible, with a random number representing physical properties intrinsic to the semiconductor chip and providing copy protection. When another semiconductor chip uses the distribution of the retrieved redundant addresses the another semiconductor chip will malfunction. The test circuit outputs a random number generated from the distribution of the retrieved redundant addresses according to a specification code received from a physical-chip-identification measuring device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.