Patent · US Active

Semiconductor transistor having superlattice structures

US10460931B2 · kind B2 · utility

0Cited by

1References

11Claims

0Family size

Assignee

Robert Bosch GmbH · DE

Inventors

Christian Tobias Banzhaf · Laichingen, DE
Martin Rambach · Neckartenzlingen, DE
Michael Grieb · Renningen, DE
Thomas Jacke · Lörrach, DE

Key dates

Filing date	Oct 19, 2016
Grant date	Oct 29, 2019
Priority date	—
Expiry date	Oct 19, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/144
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A transistor, including a substrate of a first doping type; an epitaxy layer of the first doping type above the substrate; a channel layer of a second doping type, differing from the first doping type, above the epitaxy layer; a plurality of trenches in the channel layer, which have a gate electrode situated below the trenches and are bordered by a source terminal of the first doping type above the channel layer; a plurality of shielding areas of the second doping type, which are situated below the gate electrode. The shielding areas are guided below the trenches together in a interconnection of shielding areas, and several shielding areas are jointly guided to terminals for contacting the shielding areas.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.