Fully depleted semiconductor on insulator transistor with enhanced back biasing tunability
US10460944B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Technologies for providing a semiconductor device, which can comprise a fully depleted semiconductor on insulator transistor and a method for forming the same are described. Various embodiments disclose a buried dielectric layer coupled to a semiconductor layer, and a back-gate stack is coupled to the buried dielectric layer, the back-gate stack comprising a back-gate conductor layer, a ferroelectric material layer coupled to the back-gate conductor layer, and a back-gate contact layer coupled to the ferroelectric material layer. A gate insulator can be coupled to the semiconductor layer, and a gate can be coupled to the gate insulator; the semiconductor layer can comprise a source, a drain and a channel region between the source and the drain. The negative capacitance property of the ferroelectric insulator provides back biasing of the fully depleted semiconductor on insulator transistor, including if using a relatively thick buried dielectric layer and a normal operating voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.