Semiconductor device including via plug and method of forming the same
US10461027B2 · kind B2 · utility
4Cited by
12References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2018 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Jun 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.