Semiconductor package structure
US10461035B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 20, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.