Low power clock gating circuit
US10461747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Sep 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/134
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock gating circuit is disclosed. The clock gating circuit includes an input circuit configured to receive an enable signal and clock enable circuitry configured to receive an input clock signal. The clock gating circuit also includes a latch that captures and stores an enabled state of the enable signal when the enable signal is asserted. An output circuit is coupled to the latch, and provides an output signal corresponding to a state of the clock signal when the latch is storing the enabled state. The clock gating circuit is arranged such that, when the latch is not storing the enabled state, no dynamic power is consumed responsive to state changes of the input clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.