Method and apparatus for nearest potential store tagging
US10467010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 2014 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Dec 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.