Mohammad Abdallah
92Patents
22h-index
43Co-inventors
88Inventor score
Filing activity: Mar 31, 1998 → Jul 14, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6754812B1 | Hardware predication for conditional instruction path branching | Physics | 131 | Expired |
| US6718440B2 | Memory access latency hiding with hint buffer | Physics | 128 | Expired |
| US6377970B1 | Method and apparatus for computing a sum of packed data elements using SIMD multiply circuitry | Physics | 121 | Expired |
| US6041404A | Dual function system and method for shuffling packed data elements | Physics | 115 | Expired |
| US6115812A | Method and apparatus for efficient vertical SIMD computations | Physics | 103 | Expired |
| US6282554A | Method and apparatus for floating point operations and format conversion operations | Electricity | 71 | Expired |
| US6292815A | Data conversion between floating point packed format and integer scalar format | Electricity | 62 | Expired |
| US7430656B2 | System and method of converting data formats and communicating between execution units | Physics | 60 | Expired |
| US6192467A | Executing partial-width packed data instructions | Physics | 60 | Expired |
| US6247116A | Conversion from packed floating point data to packed 16-bit integer data in different architectural registers | Physics | 47 | Expired |
| US6918032B1 | Hardware predication for conditional instruction path branching | Physics | 44 | Expired |
| US6233671A | Staggering execution of an instruction by dividing a full-width macro instruction into at least two partial-width micro instructions | Physics | 41 | Expired |
| US6122725A | Executing partial-width packed data instructions | Physics | 41 | Expired |
| US6243803A | Method and apparatus for computing a packed absolute differences with plurality of sign bits using SIMD add circuitry | Physics | 38 | Expired |
| US6266769A | Conversion between packed floating point data and packed 32-bit integer data in different architectural registers | Electricity | 35 | Expired |
| US6502115B2 | Conversion between packed floating point data and packed 32-bit integer data in different architectural registers | Electricity | 35 | Expired |
| US7133040B1 | System and method for performing an insert-extract instruction | Physics | 35 | Expired |
| US6426746B2 | Optimization for 3-D graphic transformation using SIMD computations | Physics | 32 | Expired |
| US6263426A | Conversion from packed floating point data to packed 8-bit integer data in different architectural registers | Physics | 32 | Expired |
| US7216138B2 | Method and apparatus for floating point operations and format conversion operations | Electricity | 30 | Expired |
| US6085312A | Method and apparatus for handling imprecise exceptions | Physics | 29 | Expired |
| US6480868B2 | Conversion from packed floating point data to packed 8-bit integer data in different architectural registers | Physics | 28 | Expired |
| US7761694B2 | Execution unit for performing shuffle and other operations | Physics | 17 | Active |
| US6269386A | 3X adder | Physics | 15 | Expired |
| US7516307B2 | Processor for computing a packed sum of absolute differences and packed multiply-add | Physics | 13 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.