Memory module, memory system including the same, and error correcting method thereof
US10467091B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Nov 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An error correcting method of a memory system includes: reading read data and an error correction code from a plurality of memory chips; correcting an error of the read data using the error correction code; temporarily storing the read data and the error correction code in a buffer when the correcting of the error fails; writing a certain input test pattern in the plurality of memory chips, reading an output test pattern written in the plurality of memory chips, and detecting a fail chip in which a chipkill occurs; recorrecting, based on a location of the detected fail chip, the error of the read data stored in the buffer using the error correction code stored in the buffer; and rewriting error-corrected read data and the error correction code in the plurality of memory chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.