Patent · US Active

Caching policies for processing units on multiple sockets

US10467138B2 · kind B2 · utility

1Cited by

0References

20Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Paul Blinzer · Bellevue, US
Ali Ibrahim · Sunnyvale, US
Benjamin T. Sander · Austin, US
Vydhyanathan Kalyanasundharam · Santa Clara, US

Key dates

Filing date	Dec 28, 2015
Grant date	Nov 5, 2019
Priority date	—
Expiry date	Nov 5, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/621
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.