High resistivity silicon-on-insulator structure and method of manufacture thereof
US10468295B2 · kind B2 · utility
2Cited by
20References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer structure is provided, the multilayer structure comprising a semiconductor on insulator structure comprises an insulating layer that enhances the stability of the underlying charge trapping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.